Test Pattern Generation for Crosstalk Faults in DSM Chips using Modified PODEM

Continuous increase of operating frequencies and reduction of process geometries and thereby, increase of device density in DSM chips give rise to Signal Integrity problems. Owing to higher aspect ratios of interconnects, nowadays, the coupling noise between adjacent interconnects has become major SI issue giving rise to crosstalk failures. Due to process variations and manufacturing defects, it is impossible to predict crosstalk related faults accurately even though several design techniques have been followed in the design stage. Therefore, testing the chips is essential for various faults including the crosstalk faults to ensure the quality. This paper presents an elegant way to generate test patterns for crosstalk faults using modified PODEM algorithm. In order to test crosstalk faults we need specific signal transitions at aggressor and victim lines, which are obtained through suitable transitions applied at primary inputs. Here, we divide the transitions into two logic symbols as before transitions and after transitions. We generate test patterns individually to excite the required logics both at aggressor and victim and to propagate the effect at victim to at least one primary output. Then combining them will give the transition test vector for crosstalk fault. Some benchmark circuits have been simulated by injecting the faults manually into the circuit description using XILINX for validating the generated test vectors.